Isolated bidirectional active-half-bridge resonant dc-dc power converter

ABSTRACT

An isolated bidirectional active-half-bridge resonant DC-DC power conversion apparatus employs dual control strategies to regulate bi-directional power flow between two DC sources. The apparatus includes a first half bridge switching network configured to convert a first DC power to an AC power. A series resonant impedance transfers the AC power to a first winding of a transformer. A first inductor and a second inductor are connected in series across a second winding of the transformer and form a positive DC node. A second half bridge switching network is connected in parallel with a first clamping capacitor, with a central node connected to the first end of the second winding. A third half bridge switching network is connected in parallel with a second clamping capacitor, with a central node connected with the second end of the second winding. The clamping capacitors are connected with a negative DC node.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of International Application No.PCT/EP2021/052486, filed on Feb. 3, 2021, the disclosure if which ishereby incorporated by reference in its entirety.

TECHNICAL FIELD

The aspects of the embodiments relate to power conversion apparatus andresonant DC-DC power converters.

BACKGROUND

DC-DC power converters having variable input and output voltages areuseful in a wide variety of power conversion and distributionapplications. These include for example, AC-DC rectifier systems used topower telecommunications equipment, DC-AC inverter systems as used inphotovoltaic applications, and other DC-DC conversion applications.

DC-DC converter applications may achieve optimal and efficientperformance when operating with wide-range input output voltagecapability, bi-directional power flow, zero-voltage switching (ZVS),minimum root-mean-square (rms) current through the transformer, and easein control. High power density and reliability are achieved when a DC-DCconverter is operated without DC bias in the transformer currents, withsmall current ripple at the low voltage (LV) side output, a reducednumber of switching devices, and reduced number of magnetic components.

Conventional solutions based on pure inductive impedances suffer fromhigher current stresses, higher order harmonics, and difficultyachieving ZVS with minimum rms transformer current. ZVS operation cancreate non-zero current ripple in the LV side requiring larger outputcapacitors thereby lowering power density. Bi-directional operation ofthese conventional solutions requires additional DC current blockingcapacitors.

Other solutions based on resonant impedances having two inductors and acapacitor (LLC) suffer similar drawbacks including complex controlleading to the need for additional filter capacitors and DC blockingcapacitors. Higher order impedances, such as LLCL configurations, failto solve the above-mentioned drawbacks and further reduce power densitydue to the additional impedance elements.

Thus, there is a need for improved DC-DC power converters havingsimplified control strategies, high efficiency, and high power density.Accordingly, it would be desirable to provide an apparatus thataddresses at least some of the problems described above.

SUMMARY

The aspects of the embodiments are directed to an isolated bidirectionalactive-half-bridge resonant (AHBR) DC-DC power conversion apparatusemploying a controller having dual compensation schemes configured toregulate bi-directional power flow between two DC power sources. Theaspects of the embodiments provide efficient high-density DC-DC powerconversion enhanced by a novel dual mode controller design strategy.

According to a first aspect, the above and further objectives andadvantages are obtained by an apparatus. In one embodiment, theapparatus includes a first switching network connected between a firstpositive DC node and a first negative DC node, the first switchingnetwork including a first switching device connected in series with asecond switching device and forming a first central node. A resonantinductor, a resonant capacitor, and a first winding of a transformer areconnected in series between the first central node and the firstnegative DC node. A first inductor and a second inductor are connectedin series between a first end and a second end of a second winding ofthe transformer and form a second positive DC node between the firstinductor and the second inductor. A second switching network isconnected in parallel with a first clamping capacitor, where the secondswitching network includes a third switching device connected in serieswith a fourth switching device thereby forming a second central node,where the second central node is connected with the first end of thesecond winding of the transformer. A third switching network isconnected in parallel with a second clamping capacitor, where the thirdswitching network includes a fifth switching device connected in serieswith a sixth switching device and forming a third central node, wherethe third central node is connected with the second end of the secondwinding of the transformer. The first clamping capacitor and the secondclamping capacitor are connected with a second negative DC node. Theforgoing arrangement of switching networks and power components resultsin a reduced number of switching devices and provides for simplifiedcontrol of the power flow through the apparatus.

In a first possible implementation form of the apparatus according tothe first aspect, the first inductor has the same inductance as thesecond inductor. Using the same inductive value for both of the firstand second inductor creates similar but opposite ripple currents in bothinductors allowing the ripple currents to cancel each other resulting insignificantly reduced ripple current at the output.

In a second possible implementation form of the apparatus, an inductanceof the first inductor is determined based on a maximum current andminimum voltage of the second DC power, a switching frequencycorresponding to the maximum current and minimum voltage, and aparasitic capacitance of any of the third, fourth, fifth, and sixthswitching devices. Selecting the inductor value in this way ensures zerovoltage switching operation of switches in the second and thirdswitching networks.

In a third possible implementation form of the apparatus, the apparatusincludes a first DC power source connected between the first positive DCnode and the first negative DC node, and a second DC power sourceconnected between the second positive DC node and the second negative DCnode. Including the power sources within the apparatus can aid analysisand design of the converter.

In a fourth possible implementation form of the apparatus, the firstswitching network is operated to create a first AC voltage across thefirst central node and the first negative DC node, and the secondswitching network and the third switching network are operated to createa second AC voltage across the second central node and the third centralnode. Creating AC voltages at these nodes promotes efficient powertransfer through the resonant and magnetic components of the apparatus.

In a fifth possible implementation form of the apparatus, the secondswitching network and the third switching network are operated at afifty percent duty cycle. Operating the second and third switchingnetworks at a fifty percent duty cycle ensures ripple currents generatedin the first and second inductors cancel each other.

In a sixth possible implementation form of the apparatus, the apparatusincludes a controller configured to receive a first DC voltagecorresponding to the first DC power source and a second DC voltagecorresponding to the second DC power source. The controller includes afirst control loop configured to determine a switching frequency basedon a controlled voltage and a reference voltage, and a second controlloop configured to determine a phase shift between the first AC voltageand the second AC voltage based on the controlled voltage, the referencevoltage, and a gain, where the gain is determined based on a voltage ofthe first DC power and a voltage of the second DC power. A controlsignal generator is included in the controller, where the control signalgenerator is configured to receive the switching frequency and the phaseshift and generate control signals adapted to operate the firstswitching network, the second switching network, and the third switchingnetwork in accordance with the switching frequency and the phase shift.The use of multiple control loops provides effective and efficientcontrol over a wide range of operating conditions.

In a seventh possible implementation form of the apparatus, thecontrolled voltage is proportional to one of the voltage of the first DCpower, the voltage of the second DC power, a current of the first DCpower, and a current of the second DC power. Using different values forthe controlled voltage allows the converter to be operated to producebi-directional power flow in either voltage controlled or currentcontrolled modes with a single controller architecture.

In an eighth possible implementation form of the apparatus thecontroller is configured to, when the determined switching frequency isbelow a predetermined maximum switching frequency, generate the controlsignals based on the switching frequency. When the determined switchingfrequency is not below the predetermined maximum switching frequency thecontroller is configured to generate the control signals based on themaximum switching frequency. Limiting the maximum switching frequencyensures the converter is operated within a desired range of switchingfrequencies over a wider operating range resulting in more efficientoperation.

In a ninth possible implementation form of the apparatus when thedetermined switching frequency is below the predetermined maximumswitching frequency, the phase shift is generated based on the gain, andwhen the determined switching frequency is not below the predeterminedmaximum switching frequency, the phase shift is generated based on adifference between the controlled voltage and the reference voltage.Switching between frequency and phase-controlled modes of operationprovides efficient control over a wider range of operating conditions ascompared to a single mode control scheme.

In a tenth possible implementation form of the apparatus the phase shiftis set to an inverse cosine of the gain when the gain is less than afirst threshold value; a predetermined minimum phase shift when the gainis between the first threshold value and a second threshold value, andan inverse cosine of an inverse of the gain when the gain is greaterthan a second threshold value. Control of the phase shift ensures zerovoltage switching across a wider range of operating conditions andresults in zero current switching where zero voltage switching is notpossible.

In an eleventh possible implementation form of the apparatus, the firstthreshold value is determined based on a parasitic capacitance of any ofthe first switching device and the second switching device, and apredetermined minimum value of an output current at the second DC powersource. The second threshold value is an inverse of the first thresholdvalue. Selection of the threshold values in this fashion improves zerovoltage switching operation of the converter.

In a twelfth possible implementation form of the apparatus, theparasitic capacitance of the first switching device is equal to theparasitic capacitance the second switching device. Using matchedswitching devices aids zero voltage switching in both switching devicesacross the entire operation region of the converter.

In a thirteenth possible implementation form of the apparatus, theparasitic capacitance of each of the third, fourth, fifth, and sixthswitching devices is the same. Using matched devices aids zero voltageswitching.

These and other aspects, implementation forms, and advantages of theexemplary embodiments will become apparent from the embodimentsdescribed herein considered in conjunction with the accompanyingdrawings. It is to be understood, however, that the description anddrawings are designed solely for purposes of illustration and not as adefinition of the limits of the embodiments. Additional aspects andadvantages of the disclosure will be set forth in the description thatfollows, and in part will be clear from the description, or may beunderstood by practice of the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments will be explained in more detail with reference to thedrawings, in which like references indicate like elements and:

FIG. 1 illustrates a block diagram of an exemplary DC-DC converterincorporating aspects of the embodiments;

FIG. 2 illustrates graphs showing primary waveforms for an isolatedbidirectional DC-DC power converter incorporating aspects of theembodiments;

FIG. 3 illustrates a graph showing the relationship between a gainacross the resonant network and a phase shift DC-DC power converterincorporating aspects of the embodiments;

FIG. 4 illustrates a block diagram of an exemplary control scheme for aDC-DC power converter incorporating aspects of the embodiments;

FIG. 5 illustrates graphs showing gain characteristics in thefrequency-controlled operating region of an AHBR DC-DC power converterincorporating aspects of the embodiments;

FIG. 6 illustrates a graph showing a relationship between phase shiftand output current of an AHBR DC-DC power converter incorporatingaspects of the embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring to FIG. 1 , a simplified block diagram of a power conversionapparatus 100 is illustrated. The apparatus 100 of the embodiments isdirected to an isolated bidirectional AHBR DC-DC power conversionapparatus employing a controller 150 having dual compensation schemes152, 154 configured to regulate power flow between two DC power sourcesP₁, P₂. The apparatus 100 is appropriate for use as a DC-DCconverter/conversion stage of an AC-DC rectifier system fortelecommunication equipment, or a DC-AC inverter system for photovoltaic(PV) applications, or other applications that may benefit from efficienthigh-density DC-DC power conversion.

In the example of FIG. 1 , the apparatus 100 includes a first switchingnetwork 106 connected between a first positive DC node 112 and a firstnegative DC node 114. The first switching network 106 has a firstswitching device S₁ connected in series with a second switching deviceS₂. The connection between the first switching device S₁ and the secondswitching device S₂ forms a first central node 116.

A resonant inductor Lr, a resonant capacitor Cr, and a first winding 118of a transformer Tr are connected in series between the first centralnode 116 and the first negative DC node 114. A first inductor La and asecond inductor Lb are connected in series between a first end 130 and asecond end 132 of a second winding 120 of the transformer Tr. Thisconnection forms a second positive DC node 126 between the firstinductor La and the second inductor Lb.

A second switching network 108 is connected in parallel with a firstclamping capacitor Ca, the second switching network 108 has a thirdswitching device S₃ connected in series with a fourth switching deviceS₄. The connection between the third switching device S₃ and the fourthswitching device S4 forms a second central node 122. The second centralnode 122 is connected with the first end 130 of the second winding 120of the transformer Tr.

A third switching network 110 is connected in parallel with a secondclamping capacitor Cb. The third switching network 110 includes a fifthswitching device S₅ connected in series with a sixth switching deviceS₆. The connection of the fifth switching device S₅ with the sixthswitching device S₆ forms a third central node 124. The third centralnode 124 is connected with the second end 132 of the second winding 120of the transformer Tr. The first clamping capacitor Ca and the secondclamping capacitor Cb are connected with a second negative DC node 128.

The apparatus 100 includes power handling components 140, also referredto herein as a converter topology, configured to transfer electric powerbetween a first DC power source P₁ and a second DC power source P₂. Acontroller 150 is included in the apparatus 100 and is configured toregulate bi-directional power flow between the first DC power source P₁and the second DC power source P₂ by appropriately operating threeswitching networks 106, 108, 110, referred to herein as a first, secondand third switching networks, respectively. The converter topology 140includes a high voltage (HV) side 102 and a low voltage (LV) side 104coupled together through a series impedance Z_(r), also referred toherein as a series resonant impedance, and a transformer T_(r).

As an aid to understanding, the first DC power source P₁ and the secondDC power source P₂ are included within the converter topology 140.However, those skilled in the art will readily recognize that one orboth of the DC power sources P₁ and P₂ may be implemented externally tothe apparatus 100 without straying from the spirit and scope of thepresent embodiments. For example, in one embodiment the first DC powersource P₁ may be a rectification stage, such as a power factor correctedAC-DC conversion stage, configured to convert AC grid power to DC powerand as such may be implemented as a separate power conversion stagecoupled to the converter topology 140.

The HV side 102 includes the first switching network 106 connectedbetween the first positive DC node 112 and the first negative DC node114. The first switching network 106, also referred to as a half bridgeswitching network, includes the first switching device S₁ connected inseries with a second switching device S₂, forming the first central node116 disposed between the first S₁ and second S₂ switching devices. Inthe exemplary embodiment illustrated in FIG. 1 , the first switchingdevice S₁ and the second switching device S₂ are N-channel metal oxidesemiconductor field effect transistors (MOSFET). Also illustrated arethe body diodes D₁, D₂, and parasitic output capacitances C_(OSS1),C_(OSS2) typical of many MOSFET type switching devices. Alternatively,any suitable switching device capable of efficiently switching the firstDC power P₁ at the desired frequencies may be advantageously employed asswitching devices S₁ and S₂ in the first switching network 106. Incertain embodiments, it may be advantageous to implement both switchingdevices S₁ and S₂ using the same type of switching device. This resultsin each switching device, S₁ and S₂, having the same parasitic outputcapacitance C_(OSS1)=C_(OSS2), which as will be discussed further below,has benefits with regard to zero voltage switching (ZVS).

A first DC power source P₁ may be coupled between the first positive DCnode 112 and the first negative DC node 114 and be configured to provideor receive DC power to or from the first half bridge switching network106. As used herein the term power source refers to any appropriatepower device capable of providing and/or receiving DC power. An exampleof an appropriate DC power source is a battery. A battery coupled to thefirst DC power P₁ may receive DC power from the apparatus 100 whilebeing charged and can also provide DC power when the apparatus 100 istransferring power to the second DC power source P₂.

In one embodiment a DC-link capacitor C_(L1) may be advantageouslyconnected in parallel with the first switching network 106. Including aDC-link capacitor C_(L1) can provide advantages such as smoothing andconditioning of DC power across the first switching network 106.

The first switching network 106 is coupled to a transformer T_(r)through a series resonant impedance Z_(r), where the series resonantimpedance Z_(r) includes a resonant inductor L_(r) connected in serieswith a resonant capacitor C_(r). The series resonant impedance Z_(r) isadapted to exhibit a resonant frequency f_(r). This resonance allows again to be adjusted by varying the switching frequency f_(s) ofswitching networks 106, 108, 110 in the converter topology 140. Theseries resonant impedance Z_(r) and a first winding 118 of thetransformer T_(r) are connected in series between the first central node116 and the first negative DC node 114. The resonant frequency f_(r) ofthe series resonant impedance Z_(r) is set below a pre-determinedminimum switching frequency f_(s) of the three switching networks 106,108, 110.

The transformer T_(r) includes a first winding 118 and a second winding120 with a turn ratio between the first 118 and second 120 windings of Nto one, N:1. In the illustrated embodiment 100, N is greater than onethereby making the first winding 118 the HV side 102 of the transformerT_(r), and the second winding 120 the LV side 104. Alternatively, incertain embodiments a turn ratio having N less than one may beadvantageously employed. When the turn ratio N is less than one, the HVside and LV side reverse their positions, and the second winding 120becomes the HV side of the transformer T_(r) and the first winding 118becomes the LV side.

On the LV side 104, a first inductor L_(a) and a second inductor L_(b)are connected in series between a first end 130 and a second end 132 ofthe second winding 120 of the transformer T_(r). A central node 126,disposed between the first inductor L_(a) and the second inductor L_(b),forms a second positive DC node 126 which is configured to be coupledwith the second DC power source P₂. As will be discussed further below,using the same inductive value for both of the first inductor L_(a) andthe second inductor L_(b), provides benefits with regard to the ripplecurrent at the second DC power source P₂. When desired, a second DC-linkcapacitor C_(L2) may be coupled between the second positive DC node 126and the second negative DC node 128 and in parallel with the second DCpower source P₂.

Two switching networks 108, 110 are employed on the LV side 104 which,when appropriately operated, will convert the second AC voltage v_(AC2)to a DC current i_(ab) at the second positive DC node 126.

The second switching network 108 includes the third switching device S₃and the fourth switching device S₄ connected in series and forming whatmay be referred to as a half bridge switching network. The secondcentral node 122 formed between the third switching device S₃ and thefourth switching device S₄, is connected to a first end 130 of thesecond winding 120 of the transformer T_(r), and a first clampingcapacitor C_(a) is connected in parallel with the second switchingnetwork 108. One end of the first clamping capacitor C_(a) is connectedto the second negative DC node 128.

The third switching network 110 includes the fifth switching device S₅and the sixth switching device S₆ connected in series and forming thethird central node 124. The third central node is connected to a secondend 132 of the second winding 120 of the transformer T_(r). The secondclamping capacitor C_(b) is connected in parallel with the thirdswitching network 110 with one end of the second clamping capacitorC_(b) connected to the second negative DC node 128.

Output power of the exemplary apparatus 100 is regulated by a controller150 configured to receive control signals V_(DC1) and V_(DC2), andproduce six switch control signals C₁, . . . , C₆, configured to operatethe three switching networks 106, 108, 110. The first DC voltage V_(DC1)and a second DC voltage V_(DC2) are proportional to a voltage of thefirst DC power P₁ and the second DC power P₂ respectively, and eachcontrol signal C₁, . . . , C₆ is adapted to drive a corresponding oneswitching device S₁, . . . , S₆, of the three half-bridge switchingnetworks 106, 108, 110.

In certain embodiments gate drivers (not shown) may be disposed betweenthe controller 150 and the switching devices S₁, . . . , S₆, to isolatethe controller 150 from the converter topology 140. Each control signalC₁, . . . , C₆, is generated by a gate driver configured to amplify thecontrol signal while introducing a negligibly small delay.

Two control loops are included in the controller 150. A first controlloop 152 is configured to generate a switching frequency f_(s) and thesecond control loop 154 is configured to generate a phase shift θ. Theswitching frequency f_(s) and the phase shift θ, referred to herein asthe control parameters, are used to operate the three half-bridgeswitching networks 106, 108, 110 where the switching frequency f_(s)controls a frequency of the two AC voltages v_(AC1), V_(AC2) and thephase shift θ controls a phase shift between the first AC voltagev_(AC1) and the second AC voltage V_(AC1).

The two control parameters, switching frequency f_(s) and phase shift θ,are sent to a control signal generator 156, or control signal generationalgorithm, configured to generate control signals C₁, . . . , C₆ adaptedto operate the three switching networks 106, 108, 110 to produce thedesired switching frequency f_(s) and phase shift θ within the convertertopology 140.

The resonant capacitor C_(r) included in the series resonant impedanceZ_(r) acts as a blocking capacitor to remove inherent DC bias generatedby the HV side 102 of the half bridge switching network 106. On the LVside 104 the two clamped capacitors, C_(a) and C_(b), which areconnected in parallel with each of the LV side 104 switching networks108 and 110 respectively, remove the DC bias generated by the LV sideswitching networks 108, 110.

Use of a single half bridge switching network 106 on the HV side 102along with two interleaved half bridge switching networks 108, 110 onthe LV side 104 results in a power conversion apparatus 100 having areduced number of switching devices S₁-S₆ as compared to the number ofswitching devices used in many conventional power converters.

FIG. 2 illustrates graphs 200 showing the primary waveforms for anisolated bidirectional AHBR DC-DC power converter incorporating aspectsof the embodiments. The primary waveforms illustrated in graphs 200 arerepresentative of primary waveforms generated within an exemplaryisolated bidirectional AHBR DC-DC power converter such as the apparatus100 described above and with respect to FIG. 1 . In the graphs 200, timeis depicted along a horizontal axis 202 increasing to the right whilemagnitude is depicted in each of the graphs 206, 208, 210, 212, and 214along a vertical axis 204 increasing upwards.

The first two graphs 206 and 208 illustrate the six control signals C₁,. . . , C₆ generated by the controller 150 and used to operate the sixswitching devices S₁, S₂, . . . , S₆ in each of the three half-bridgeswitching networks 106, 108, 110. In the graphs 206, 208 a controlsignal with a value of one (1) turns the corresponding switching deviceon and a value of zero (0) turns the corresponding switching device off,where “on” means the switching device is conducting and “off” means theswitching device is not conducting.

Graph 206 illustrates control signals C₁ and C₂ used to operatecorresponding switching devices S₁ and S₂ in the first half-bridgeswitching network 106. The first half bridge switching network 106 isoperated at a fifty percent (50%) duty cycle where the “on” time of eachswitching device S₁, S₂ is the same. During a dead time t_(d1) bothcontrol signals C₁ and C₂ are set to zero to allow for proper switchingof the first half-bridge switching network 106.

Graph 208 illustrates control signals C₃, C₄, C₅, and C₆ used to operatecorresponding switching devices S₃, S₄, S₅, and S₆ in the twointerleaved half-bridge switching networks 108 and 110. The secondhalf-bridge switching network 108 and the third half-bridge switchingnetwork 110 are operated at a fifty percent (50%) duty cycle where the“on” time of each switch S₃, S₄, S₅, and S₆ is the same. A dead timet_(d2), where all four control signals C₃, C₄, C₅, and C₆ are set tozero, allows for proper switching of the two interleaved half-bridgeswitching networks 108, 110.

Graph 210 illustrates the first AC voltage v_(AC1) generated by thefirst switching network 106, the second AC voltage V_(AC2) generated bythe two interleaved half bridge switching networks 108 and 110, and thecurrents i₁ and i₂ generated within the first winding 118 and the secondwinding 120 of the transformer T_(r). The first AC voltage v_(AC1)varies between the voltage V₁ of the first DC power source P₁ and zerovolts. The second AC voltage V_(AC2) varies between twice the voltage V₂of the second DC power source P₂, labelled as 2V₂ in graph 210, and anequal negative voltage −2V₂. The AC voltages v_(AC1) and v_(AC2) createa nearly sinusoidal current i₁ through the resonant inductor L_(r).Power flow through the converter is controlled by the phase shift θbetween the first AC voltage v_(AC1) and the second AC voltage v_(AC2).

As can be seen in the graph 210, the AC voltages v_(AC1) and v_(AC2)creates a nearly sinusoidal current i₁ by exciting the series resonantimpedance Z_(r). A second current i₂ flowing through the second winding120 (not shown in the graph 210) has the same nearly sinusoidal shape asthe first current i₁. The near sinusoidal nature of currents i₁ and i₂reduces current stresses on the power handling components 140 and alsoreduces high-order harmonics, thereby lowering conduction and corelosses in the transformer T_(r).

Graph 212 illustrates voltages v_(La) and v_(Lb) applied to the twoinductors L_(a) and L_(b), along with the corresponding currents i_(La)and i_(Lb) flowing through the two inductors L_(a) and L_(b),respectively. The second AC voltage v_(AC2) generated by the twointerleaved switching networks 108, 110 applies an AC voltage v_(La) andv_(Lb) to each inductor that varies between the voltage V₂ of the secondDC power source P₂ and the negative of that voltage −V₂. As can be seenin the graph 212, the two AC inductor voltages v_(La) and v_(Lb) haveopposite polarity resulting in similarly shaped but opposite ripplecurrents i_(La) and i_(Lb) flowing through each inductor.

The current i_(ab) flowing to the second DC power source P₂ isillustrated in the bottom graph 214. The similarly shaped but oppositeripple currents i_(La) and i_(Lb) flowing through the two inductorsL_(a) and L_(b) cancel each other leaving a substantially ripple free DCcurrent i_(ab) which in certain embodiments becomes the output currentof the second DC power source I_(o2). Appropriate selection of valuesfor the two inductors reduces ripple current at the output I_(o2) andallows for a very small value link capacitor C_(L2).

Creating an efficient and dense power converter requires both a suitableconverter topology as well as an efficient control scheme. The convertertopology 140 described above and with reference to FIG. 1 and FIG. 2provides such a suitable converter topology. The following analysis willprovide a basis for a simple and efficient control scheme.

As an aid to understanding, the converter topology 140 will be analysedby considering a forward power flow from the first DC power source P₁ onthe HV side 102 to the second DC power source P₂ on the LV side 104 ofthe converter topology 140. The reverse power flow behaves similarly andan analysis of the reverse power flow follows directly from analysis ofthe forward power flow shown below. Symbols in the following analysiscorrespond to the elements of the apparatus 100 illustrated in FIG. 1and described above.

Applying fundamental component analysis to the converter topology 140yields the average power P₂ and current I_(o2) at the LV side 104 shownin the following equations (1) and (2):

$\begin{matrix}{{P_{2} = \frac{2V_{1}^{2}M\sin\theta}{\pi^{2}Z_{r}}},} & (1)\end{matrix}$ $\begin{matrix}{{I_{o2} = \frac{8{NV}_{1}\sin\theta}{\pi^{2}Z_{r}}},} & (2)\end{matrix}$

where θ is the phase shift between the first AC voltage v_(AC1) and thesecond AC voltage v_(AC2). Varying the phase shift θ over the range−π/2≤θ≤+π/2 determines the direction and magnitude of power and currentflow between the HV side 102 and the LV side 104 of the apparatus 100. Apositive phase shift θ causes power to flow from the HV side 102 to theLV side 104, and a negative phase shift −0 reverses the power flow.

Gain M across the resonant impedance Z_(r) varies with the switchingfrequency f_(s) and is given by equation (3):

$\begin{matrix}{M = {\frac{4{NV}_{AC2}}{V_{AC1}}.}} & (3)\end{matrix}$

The value of the resonant impedance Z_(r) is shown in equation (4):

$\begin{matrix}{Z_{r} = {{2\pi f_{s}L_{r}} - {\frac{1}{2\pi f_{s}C_{r}}.}}} & (4)\end{matrix}$

Conduction losses in the apparatus 100 are dependent on the root meanssquare (RMS) values of a first current i₁ and a second current i₂, wherethe first current i₁ and second current i₂ are related by thetransformer turn ratio N such that the first current i₁ is equal to theturn ratio N times the second current i₂, (i₁=N i₂). The RMS value ofthe of the first current I_(1rms) is given by equation (5):

$\begin{matrix}{{I_{1rms} = \frac{\pi I_{o2} \times \sqrt{{2M^{2}} - {4M\cos\theta} + 2}}{8N\sin\theta}},} & (5)\end{matrix}$

where the second current I_(o2) is the current flowing through thesecond power P₂, which for the purposes of this analysis will bereferred to as the output current.

It is important to minimize circulating currents during converteroperation. To obtain the minimum circulating current, the firstderivative with respect to phase shift θ of a ratio between the RMSvalue of the first current I_(1rms) and the output current I_(o2) is setto zero. Solving for the required values of phase shift θ yields theresult is shown in equation (6):

$\begin{matrix}{{\frac{\partial}{\partial\theta}\left( \frac{I_{1rms}}{I_{o2}} \right)} = {{0\overset{yields}{\rightarrow}\theta} = \left\{ {\begin{matrix}{\cos^{- 1}M} & {{{for}\ M} \leq 1} \\{\cos^{- 1}\frac{1}{M}} & {{{for}\ M} > 1}\end{matrix}.\begin{matrix}\  \\\text{  }\end{matrix}} \right.}} & (6)\end{matrix}$

Substituting the result in equation (6) into equation (5) gives arelationship between the minimum RMS value of the first currentI_(1rm,min) and the output current I_(o2) as shown in equation (7):

$\begin{matrix}{I_{{1{rms}},\min} = {\frac{I_{{2{rms}},\min}}{N} = \left\{ {\begin{matrix}\frac{\pi I_{o2} \times \sqrt{2}}{8N} & {{{for}\ M} \leq 1} \\\frac{\pi{MI}_{o2} \times \sqrt{2}}{8N} & {{{for}\ M} > 1}\end{matrix}.} \right.}} & (7)\end{matrix}$

Equation (7) shows that for gain M greater than 1 (M>1), the minimum RMScurrent I_(1rm,min) increases proportionally with an increase in thegain M. Therefore, in certain embodiments it may be desirable to selectthe transformer turn ratio N based on equation (3) to keep the gain Mless than or equal to 1 (M≤1). Substituting equation (6) into equation(2) gives a relationship for the output current I_(o2) as a function ofthe gain M as shown in equation (8):

$\begin{matrix}{I_{o2} = \left\{ {\begin{matrix}\frac{8{NV}_{1} \times \sqrt{1 - M^{2}}}{\pi^{2}Z} & {{{for}\ M} \leq 1} \\\frac{8{NV}_{1^{\times}}\sqrt{1 - \frac{1}{M^{2}}}}{\pi^{2}Z} & {{{for}\ M} > 1}\end{matrix}.} \right.} & (8)\end{matrix}$

An important consideration for efficient power converter design is ZVSoperation of the switching networks 106, 108, 110. With a gain of one(M=1) equation (6) shows the phase shift is zero (θ=0) and equation (8)shows the output current is zero (I_(o2)=0). To avoid this condition thephase shift θ should be limited to a minimum value in a small regionnear the gain of one (M=1). A region can be defined where the gain M isgreater than a minimum threshold value M₁ and less than a maximumthreshold value M₂, where M₁ is less than 1 and M₂ is greater than 1i.e., M₁≤M≤M₂. The phase shift θ can then be held constant within thisregion as shown in equation (9):

θ_(min)=cos⁻¹ M _(max1)  (9).

Equations (6) and (9) can be combined to give a complete definition ofthe phase shift over the full range of gain M as shown in equation (10):

$\begin{matrix}{\theta = \left\{ {\begin{matrix}{\cos^{- 1}M} & {for} & {M < M_{\max 1}} \\{\cos^{- 1}M_{\max 1}} & {for} & {M_{\max 1} \leq M \leq M_{\max 2}} \\{\cos^{- 1}\frac{1}{M}} & {for} & {M > M_{\max 2}}\end{matrix}.} \right.} & (10)\end{matrix}$

FIG. 3 illustrates a graph 300 showing the relationship between gain Mand phase shift θ in an apparatus 100 incorporating aspects of theembodiments. The graph 300 depicts the gain M along a horizontal axis302 increasing to the right, and phase shift θ in radians along avertical axis 304 increasing upward. The phase relationship 306 depictedin the graph 300 is defined by equation (10) described above. As can beseen in the graph 300, the phase shift θ is a piecewise continuous curvewith a minimum phase shift θ_(min), n being imposed in a region around again M of one.

ZVS operation of the HV side 102 switches S₁ and S₂ depends on theminimum phase shift θ_(min), or more particularly, the inductor currenti₁ during the first dead time t_(d1). This minimum phase shift θ_(min)depends on the minimum gain threshold M₁ as show in equation (11):

$\begin{matrix}{{M_{1} = \frac{\sqrt{\left( {\pi I_{{o2},\min,{zvs}}t_{d1}} \right)^{2} - \left( {8NQ_{1,\max}} \right)^{2}}}{\pi I_{{o2},\min,{zvs}}t_{d1}}},} & (11)\end{matrix}$

where I_(o2,min,zvs) is the minimum output current at LV side 104 abovewhich ZVS at HV side 102 is guaranteed, and Q_(1,max) is the maximumcharge stored on the parasitic output capacitance C_(oss1) of the firstHV side switching device S₁. The second gain threshold M₂ can now beevaluated based on equations (9) and (11) as shown in equation (12):

$\begin{matrix}{M_{2} = {\frac{1}{\cos\left( \theta_{\min} \right)} = {\frac{1}{M_{1}}.}}} & (12)\end{matrix}$

In the region between the minimum gain threshold M₁ and the maximum gainthreshold M₂, the HV side switching devices S₁ and S₂ may not be able toachieve ZVS switching. However, zero current switching (ZCS) operationcan be guaranteed. ZCS is less desirable than ZVS but is still betterthan hard switching operation.

ZVS operation for the LV-side switches S₃ through S₆ depends on currentis through the first inductor L_(a) and current i_(b) through the secondinductor L_(b). The first inductor L_(a) and the second inductor L_(b).should have equal value to minimize output current ripple. Thus, incertain embodiments the value of the first inductor L_(a) and the secondinductor L_(b). can be determined using equation (13),

$\begin{matrix}{{L_{a} = {L_{b} = \frac{V_{2,\min}t_{d2}}{2{f_{s}^{\prime}\left( {{8V_{2,\min}C_{{oss}3}} + {I_{{o2},\max}t_{d2}}} \right)}}}},} & (13)\end{matrix}$

where I_(o2,max) is the maximum output current at LV side 104, t_(ds) isthe dead time between the third and fourth switching devices S₃, S₄ andbetween the fifth and sixth switching devices S₅, S₆, V_(2, min) is thegiven minimum value of LV-side voltage V₂, f′s is the switchingfrequency to achieve the desired maximum output current I_(o2,max) atV_(2,min), and C_(oss3) is the parasitic output capacitance of theLV-side switching devices S₃, S₄, S₅, S₆.

An important consideration for design of the apparatus 100 is the choiceof the resonant impedance Z_(r). The minimum required impedance Z_(min)to deliver the desired maximum output current I_(o2,max) can becalculated for the minimum gain threshold M₁ and minimum input voltageV_(1, min) as shown in equation (14):

$\begin{matrix}{{Z_{\min} = {\frac{8{NV}_{1,\min} \times \sqrt{1 - M_{\max 1}^{2}}}{\pi^{2}I_{{o2},\max}} = {{2\pi f_{s,\min}L} - \frac{1}{2\pi f_{s,\min}C}}}},} & (14)\end{matrix}$

where V_(1,min) is the given minimum input voltage and f_(s,min) is thepredetermined minimum switching frequency.

The resonance frequency f_(r) of the resonant impedance Z_(r) should beless than the minimum desired switching frequency, f_(r)<f_(s), and isgiven by equation (15),

$\begin{matrix}{f_{r} = {\frac{1}{2\pi\sqrt{LC}}.}} & (15)\end{matrix}$

In one embodiment equations (14) and (15) may be solved simultaneouslyto determine suitable values for the resonant inductor Lr and theresonant capacitor Cr.

FIG. 4 illustrates a block diagram of an exemplary control scheme 400incorporating aspects of the embodiments. The exemplary control scheme400 is appropriate for use as the controller 150 in the apparatus 100described above and with reference to FIG. 1 .

The exemplary control scheme 400 of the embodiments includes two controlloops 452, 454 where the first control loop 452 generates a switchingfrequency f_(s), and the second control loop 454 generates a phase shiftθ. The exemplary first and second control loops 452, 454 are appropriatefor use as the first and second control loops 152, 154 described aboveand with reference to FIG. 1 . The control parameters, which areswitching frequency f_(s) and phase shift θ, are used by a controlsignal generator 456 to generate control signals C₁, . . . , C₆configured to drive three switching networks, such as the threeswitching networks 106, 108, 110 described above.

As used herein the term control loop refers to a feedback mechanismwhere a measured signal corresponding to the system output beingcontrolled is compared with a reference signal to create an errorsignal, where the error signal represents a difference between thedesired system output and the actual system output. The control loopuses the error signal to adjust values of one or more control parametersin a way that drives the actual system output toward the desired systemoutput.

In the control scheme 400, an error signal e is determined by taking thedifference between a reference voltage V_(ref), and a controlled voltageV_(c). The reference voltage V_(ref) is set based on the desired outputof the apparatus 100, and the controlled voltage V_(c) is a measuredvalue proportional to an output of the apparatus 100. The controlledvoltage V_(c) may be derived from differing system characteristics basedon the desired converter operation. For example, with power flowingforward from the first DC power source P₁ to the second DC power sourceP₂, the controlled voltage V_(c) may be set proportional to the secondDC voltage V₂, thereby regulating or controlling a voltage V₂ of thesecond DC power source P₂. During reverse operation when power isflowing from the second DC power source P₂ to the first DC power sourceP₁, the controlled voltage V_(c) may be set proportional to the first DCvoltage V₁, thereby regulating or controlling a voltage V₁ of the firstDC power source P₁. Alternatively, the control scheme 400 may beoperated in a current control mode by setting the controlled voltageproportional to either the second DC current I_(o2) or the first DCcurrent I_(o1) as desired. In the illustrated embodiment the same errorsignal e is shared by both the first control loop 452 and the secondcontrol loop 454.

The first control loop 452 applies a first compensation algorithm 412 tothe error signal e to produce a determined switching frequency f_(s PI).In the exemplary embodiment illustrated in FIG. 4 the first compensationalgorithm 412 is a proportional plus integral (PI) control algorithm.Alternatively, any suitable compensation algorithm 412 may beadvantageously employed without straying from the spirit and scope ofthe present embodiments.

A comparator 410 compares the determined switching frequency f_(sPI)produced by the compensation algorithm 412 to a pre determined maximumswitching frequency f_(s,max) and generates a logic signal x having avalue of logical zero (0) when the determined switching frequencyf_(sPI) is less than the maximum switching frequency f_(s, max) and avalue of logical one (1) otherwise. A multiplexer 406 selects theswitching frequency f_(s) based on the logic signal x. This results in aswitching frequency f_(s) equal to the determined switching frequencyf_(sPI) when the determined switching frequency f_(sPI) is less than thepre-determined maximum switching frequency f_(s, max) and a switchingfrequency f_(s) equal to the maximum switching frequency f_(s,max) whenthe determined switching frequency f_(sPI) is not less than the maximumswitching frequency f_(s, max).

During primary converter operation, referred to herein asfrequency-controlled mode, the determined switching frequency f_(sPI) isbelow the maximum switching frequency f_(s,max) and power flow isregulated by the first control loop 452. In this region, the phase shiftθ is generated based on a gain M across the series resonance Z_(r) asdescribed in equation (10). The exemplary control scheme 400 calculatesthe gain M based on the first DC voltage V₁ and the second DC voltage V₂using equation (3). Equation (10) is then applied along with the gain Mto determine the computed phase shift θ′. A multiplexer 408 receives thelogic signal x and sets the phase shift θ equal to the computed phaseshift θ′ when the determined switching frequency f_(sPI) is below themaximum switching frequency f_(s,max).

Direction of power flow, from the first DC power source P₁ to the secondDC power source P₂ or from the second DC power source P₂ to the first DCpower source P₁, is controlled by a direction signal D where thedirection signal is configured to change the sign of the phase shift θbased on the desired power flow. As shown in the preceding analysis, apositive phase shift causes power to flow from the first DC power sourceP₁ to the second DC power source P₂, while a negative phase shiftreverses the flow of power.

When the determined switching frequency f_(sPI) is not below the maximumswitching frequency f_(s,max), the exemplary control scheme 400 sets theswitching frequency f_(s) to the maximum switching frequency f_(s,max),and the controller 400 shifts to a phase-controlled mode. While theswitching frequency f_(s) is fixed at the maximum switching frequencyf_(s,max), the multiplexer 408 sets the phase shift θ to the determinedphase shift θ_(PI) and power flow is controlled with the determinedphase shift θ_(PI) produced by the second control loop 454.

The second control loop 454 applies a second compensation algorithm 414to the error signal e to produce a determined phase shift θ_(PI). Theexemplary embodiment 400 is illustrated as having a PI compensationalgorithm in the exemplary second compensation algorithm 414, howeverthose skilled in the art will readily recognize that any suitablecompensation algorithm may be advantageously employed in thecompensation algorithm 414 without straying from the spirit and scope ofthe present embodiments.

The control signal generator 456 receives the switching frequency f_(s)and the phase shift θ and produces control signals C₁, . . . , C₆configured to operate the three switching networks 106, 108, 110. In theexemplary control signal generator 456 the switching frequency f_(s) isinput to a voltage-controlled oscillator 402 to produce a first set ofcontrol signals C′₁, . . . , C′₆ having the desired switching frequency.Pulse width modulation 404 is then applied to the first set of controlsignals C′₁, . . . , C′₆ based on the phase shift θ to produce controlsignals C₁, C₂ to operate the first switching network 106 and controlsignals C₃, C₄, C₅, and C₆ to operate the second and third switchingnetworks 108, 110.

The exemplary control scheme 400 may be implemented using digitalcircuitry such as a microcontroller unit. Alternatively, the exemplarycontrol scheme 400 may be implemented using analog circuitry or throughany suitable combination of analog and digital circuitry.

FIG. 5 illustrates graphs 500 showing gain characteristics in thefrequency-controlled operating region of an AHBR DC-DC power converterincorporating aspects of the embodiments. The graphs 500 illustrateoperating characteristics of the control scheme 400 described above andwith reference to FIG. 4 during the frequency controlled operating modeimplemented by the first control loop 452. In the graph 500, switchingfrequency f_(s) is depicted along a horizontal axis 502 with frequencyincreasing to the right, and the gain M is depicted along a verticalaxis 504 increasing upward. The operating region forfrequency-controlled mode is shown as interval 506 along the top of thegraph 500. Each line shows the gain versus frequency curve for aparticular value of output current. For example, the line labelledI_(o2)=15A shows the gain vs frequency characteristic for an outputcurrent of fifteen (15) amps. The switching frequency f_(s) is limitedto a minimum value f_(s,min) that is above the resonant frequency f_(r)of the series resonant impedance Z_(r). As can be seen from the graph500, as output current I_(o2) decreases, the switching frequency f_(s)increases. This results in low values of output current, such asI_(o2)=0.8A, where the maximum switching frequency f_(s,max) can bereached. At that point, the control scheme 400 moves to a phase shift θcontrolled mode handled by the second control loop 454.

FIG. 6 illustrates a graph 600 showing a relationship between phaseshift and output current of an AHBR DC-DC power converter incorporatingaspects of the embodiments. The graph 600 illustrates operatingcharacteristics of the exemplary control scheme 400 when the switchingfrequency f_(s) has reached it maximum value f_(s,max) and the secondcontrol loop 454 is operating in a phase shift controlled mode. Thegraph 600 depicts phase shift in radians along a horizontal axis 602increasing to the right and output current I_(o2) in amps along ahorizontal axis 604 increasing upwards. The curve 606 shows theconditions at which the control scheme 400 will switch fromfrequency-controlled mode to phase shift-controlled mode. When thedetermined switching frequency f_(sPI) produced by the firstcompensation algorithm 412 reaches the maximum switching frequencyf_(s,max), the control scheme 400 transitions from thefrequency-controlled mode regulated by the first control loop 452 tophase shift controlled mode regulated by the second control loop 454.The circles, such as the circle 608, along the line 606 represent pointsof output current and phase shift (I_(o2), θ) which, for a particularvalue of gain M, the exemplary control scheme 400 would be required toshift from frequency-controlled mode to the phase-shift controlled mode.The second control loop 454 will then continue to reduce the phase shiftθ until the desired output current I_(o2) is reached.

Thus, while there have been shown, described and pointed out,fundamental novel features of the embodiments thereof, it will beunderstood that various omissions, substitutions and changes in the formand details of devices and methods illustrated, and in their operation,may be made by those skilled in the art without departing from thespirit and scope of the embodiments. Further, it is expressly intendedthat all combinations of those elements, which perform substantially thesame function in substantially the same way to achieve the same results,are within the scope of the embodiments. Moreover, it should berecognized that structures and/or elements shown and/or described inconnection with any form or embodiment may be incorporated in any otherdescribed or suggested form or embodiment.

1. An apparatus comprising: a first switching network connected between a first positive DC node and a first negative DC node, the first switching network comprising a first switching device connected in series with a second switching device and forming a first central node; a resonant inductor, a resonant capacitor, and a first winding of a transformer connected in series between the first central node and the first negative DC node; a first inductor and a second inductor connected in series between a first end and a second end of a second winding of the transformer, and forming a second positive DC node between the first inductor and the second inductor; a second switching network connected in parallel with a first clamping capacitor, the second switching network comprising a third switching device connected in series with a fourth switching device and forming a second central node, wherein the second central node is connected with the first end; and a third switching network connected in parallel with a second clamping capacitor, the third switching network comprising a fifth switching device connected in series with a sixth switching device and forming a third central node, wherein the third central node is connected with the second end; wherein the first clamping capacitor and the second clamping capacitor are connected with a second negative DC node.
 2. The apparatus according to claim 1, wherein an inductance of the first inductor is equal to an inductance of the second inductor.
 3. The apparatus according to claim 2, further comprising: a first DC power source connected between the first positive DC node and the first negative DC node; and a second DC power source connected between the second positive DC node and the second negative DC node.
 4. The apparatus according to claim 3, wherein the inductance of the first inductor is determined based on a maximum current and a minimum voltage of the second DC power, switching frequency corresponding to the maximum current and the minimum voltage, and a parasitic capacitance of any of the third, fourth, fifth, and sixth switching devices.
 5. The apparatus according to claim 4, wherein the first switching network is configured to create a first AC voltage across the first central node and the first negative DC node; and the second switching network and the third switching network are configured operated to create a second AC voltage across the second central node and the third central node.
 6. The apparatus according to claim 5, wherein the second switching network and the third switching network are configured to operated at a fifty percent duty cycle.
 7. The apparatus according to claim 3, further comprising: a controller configured to receive a first DC voltage corresponding to the first DC power source and a second DC voltage corresponding to the second DC power source, the controller comprising: a first control loop configured to determine a switching frequency based on a controlled voltage and a reference voltage; a second control loop configured to determine a phase shift between the first AC voltage and the second AC voltage based on the controlled voltage, the reference voltage, and a gain, wherein the gain is determined based on a first voltage of the first DC power and a second voltage of the second DC power; and a control signal generator configured to receive the switching frequency and the phase shift and generate control signals configured to operate the first switching network, the second switching network, and the third switching network in accordance with the switching frequency and the phase shift.
 8. The apparatus according to claim 4, further comprising: a controller configured to receive a first DC voltage corresponding to the first DC power source and a second DC voltage corresponding to the second DC power source, the controller comprising: a first control loop configured to determine a switching frequency based on a controlled voltage, and a reference voltage; a second control loop configured to determine a phase shift between the first AC voltage and the second AC voltage based on the controlled voltage, the reference voltage, and a gain, wherein the gain is determined based on a first voltage of the first DC power and a second voltage of the second DC power; and a control signal generator configured to receive the switching frequency and the phase shift and generate control signals configured to operate the first switching network, the second switching network, and the third switching network in accordance with the switching frequency and the phase shift.
 9. The apparatus according to claim 5, further comprising: a controller configured to receive a first DC voltage corresponding to the first DC power source and a second DC voltage corresponding to the second DC power source, the controller comprising: a first control loop configured to determine a switching frequency based on a controlled voltage, and a reference voltage; a second control loop configured to determine a phase shift between the first AC voltage and the second AC voltage based on the controlled voltage, the reference voltage, and a gain, wherein the gain is determined based on a first voltage of the first DC power and a second voltage of the second DC power; and a control signal generator configured to receive the switching frequency and the phase shift and generate control signals configured to operate the first switching network, the second switching network, and the third switching network in accordance with the switching frequency and the phase shift.
 10. The apparatus according to claim 7, wherein the controlled voltage is proportional to one of the first voltage, the second voltage, a current of the first DC power, and a current of the second DC power.
 11. The apparatus according to claim 8, wherein the controlled voltage is proportional to one of the first voltage, the second voltage, a current of the first DC power, and a current of the second DC power.
 12. The apparatus according to claim 7, wherein, when the determined switching frequency is below a predetermined maximum switching frequency, the control signals are generated based on the switching frequency, and when the determined switching frequency is not below the predetermined maximum switching frequency, the control signals are generated based on the maximum switching frequency.
 13. The apparatus according to claim 8, wherein, when the determined switching frequency is below a predetermined maximum switching frequency, the control signals are generated based on the switching frequency, and when the determined switching frequency is not below the predetermined maximum switching frequency, the control signals are generated based on the maximum switching frequency.
 14. The apparatus according to claim 10, wherein, when the determined switching frequency is below a predetermined maximum switching frequency, the control signals are generated based on the switching frequency, and when the determined switching frequency is not below the predetermined maximum switching frequency, the control signals are generated based on the maximum switching frequency.
 15. The apparatus according to claim 11, wherein, when the determined switching frequency is below a predetermined maximum switching frequency, the control signals are generated based on the switching frequency, and when the determined switching frequency is not below the predetermined maximum switching frequency, the control signals are generated based on the maximum switching frequency.
 16. The apparatus according to claim 7, wherein when the determined switching frequency is below the predetermined maximum switching frequency, the phase shift is generated based on the gain, and when the determined switching frequency is not below the predetermined maximum switching frequency, the phase shift is generated based on a difference between the controlled voltage and the reference voltage.
 17. The apparatus (100) according to claim 10, wherein, when the determined switching frequency is below the predetermined maximum switching frequency, the phase shift is generated based on the gain, and when the determined switching frequency is not below the predetermined maximum switching frequency, the phase shift is generated based on a difference between the controlled voltage and the reference voltage.
 18. The apparatus according to claim 7, wherein: when the gain is less than a first threshold value, the phase shift is set to an inverse cosine of the gain; when the gain is between the first threshold value and a second threshold value, the phase shift is set to a predetermined minimum phase shift; and when the gain is greater than a second threshold value, the phase shift is set to an inverse cosine of an inverse of the gain.
 19. The apparatus according to claim 18, wherein: the first threshold value is determined based on a parasitic capacitance of any of the first switching device and the second switching device and a predetermined minimum value of an output current at the second DC power source; and the second threshold value is an inverse of the first threshold value.
 20. The apparatus according to claim 19, wherein the parasitic capacitance of the first switching device and the second switching device is equal. 